The present invention relates to a magnetic memory device and a method of manufacturing the same, and particularly to a method of manufacturing a non-volatile magnetic memory device, and the magnetic memory device, for recording information by utilizing the phenomenon that the resistance of a ferromagnetic material constituting a tunnel magnetoresistance device (hereinafter referred to as TMR device) varies according to whether the spin directions are parallel or antiparallel.
Attendant on the rapid popularization of information communication apparatuses, particularly, personal small apparatuses such as personal digital aids, the devices such as memory devices and logic devices constituting these apparatuses are demanded to have a further higher performance such as higher degree of integration, higher operating speed, and less power consumption. Particularly, non-volatile memories are considered to be indispensable devices for the ubiquitous computing age.
The non-volatile memories can protect important personal data even when, for example, the power source is exhausted or troubled or when a server and a network are disconnected due to some disorder. Accordingly, the enhancement of density and capacity of the non-volatile memories has come to be more and more important as a technology for substitution for hard disk and optical disk drives which cannot intrinsically be reduced in size due to the presence of movable parts.
In addition, while the recent portable apparatuses have been designed to reduce power consumption as much as possible by putting the unnecessary circuit blocks into a stand-by condition, the wasting of power consumption and memories can be precluded if a non-volatile memory functioning as both a high-speed network memory and a high-capacity storage memory is realized. Besides, the so-called instant-ON function for enabling the apparatus to be started instantaneously upon turning-on of the power source can be achieved if a high-speed high-capacity non-volatile memory is realized.
The non-volatile memories conventionally known include the flash memory using a semiconductor and the FRAM (ferroelectric random access memory) using a ferroelectric material. However, the flash memory has the defect of a slow writing speed on the order of microseconds. On the other hand, the FRAM has a number of times of overwriting possible of 1012 to 1014, which means an insufficient durability for perfect substitution for static random access memory and dynamic random access memory. Besides, there has been pointed out the problem that it is difficult to achieve micro-processing of ferroelectric material capacitors.
A memory paid attention to as a non-volatile memory which does not have the above-mentioned drawbacks is the magnetic memory called MRAM (magnetic random access memory). The MRAMs in the beginning stage have been based on spin valves using the AMR (anisotropic magnetoresistance) effect reported in J. M. Daughton, Thin Solid Films, Vol. 216 (1992), pp. 162-168, or the GMR (giant magnetoresistance) effect reported in D. D. Tang et al., IEDM Technical Digest, (1997), pp. 995-997. However, these MRAMs have the drawback that since the memory cell resistance of the load is as low as 10 to 100 Ω, the power consumption per bit at the time of reading is large and it is difficult to achieve a higher capacity.
On the other hand, as for the TMR (tunnel magnetoresistance) effect, there was once the drawback that the resistance variation factor was no more than 1 to 2% at room temperature, as reported in R. Meservey et al., Physics Reports, Vol. 238 (1994), pp. 214-217. In recent years, however, a resistance variation factor of about 20% has come to be achieved, as reported in T. Miyazaki et al., J. Magnetism & Magnetic Material, Vol. 139 (1995), L231, and attention has become focused on the MRAM using the TMR effect.
The MRAM is simple in structure, which allows an easy increase in the degree of integration, and, since recording is conducted by rotation of magnetic moment, it is predicted that the number of time of overwriting possible is large. As to access time in the MRAM, a very high speed is expected, and an operating speed of 100 MHz has already been achieved, as reported in R. Scheuerlein et al., ISSCC Digest of Technical Papers, (February 2000), pp. 128-129.
Next, a method of manufacturing an MRAM according to the related art will be described referring to the manufacturing step sectional views shown in FIGS. 3 and 4. FIGS. 3 and 4 illustrate principally the formation of a tunnel magnetoresistance device and a method of forming a connection wiring for connecting the tunnel magnetoresistance device to a conductor layer provided on the lower side thereof.
As shown in FIG. 3A, a first insulation film 41 for covering a reading transistor (not shown) is formed, and a first contact 31 for connection to a diffusion layer (not shown) of the reading transistor is formed in the first insulation film 41. Further, a sense line 15, a first landing pad 32 for connection to the first contact 31, and the like are formed on the first insulation film 41, and a second insulation film 42 for covering these components is formed. The surface of the second insulation film 42 is planarized by chemical mechanical polishing, and the second insulation film 42 is left in a thickness of 700 nm on the sense line 15 and the first landing pad 32. Furthermore, a mask layer (not shown) composed of a P-SiN film is built up in a thickness of 20 nm.
An insulation film 431 constituting a lower layer of a third insulation film 43 is formed on the mask layer. A writing word line 11 with a groove wiring structure, and a second contact 33 and a second landing pad 34 which are connected to the first landing pad 32 are formed in the insulation film 431. The writing word line 11 and the second landing pad 34 are exposed at the surface of the insulation film 431. An insulation film 432 for covering the writing word line 11 is formed by building up aluminum oxide in a thickness of 50 nm, on the insulation film 431. Thus, the insulation film 431 and the insulation film 432 constitute the third insulation film 43. The insulation film 432 on the second landing pad 34 is provided with a via hole 433 for contriving connection between a TMR device which is to be formed and the second landing pad 34.
A barrier layer (not shown), an antiferromagnetic material layer 131, a magnetization fixed layer 132 formed of a ferromagnetic material, a tunnel insulation layer 133, a storage layer 134 formed of a ferromagnetic material, and a cap layer 135 are sequentially formed in this order from the lower side by PVD (physical vapor deposition), on the third insulation film 43 with the above-mentioned structure inclusive of the via hole 433.
Next, as shown in FIG. 3B, the cap layer 135 is etched by a reactive ion etching technique with a photoresist as a mask, thereafter the photoresist is ashed, and the range from the storage layer 134 to an intermediate portion of the tunnel insulation layer 133 is etched with the cap layer 135 as a mask, to form a TMR device region 14. The finish point of etching is set in the tunnel insulation layer 133. Though not shown, the aluminum oxide film of the tunnel insulation layer 133 is left in other regions than the TMR device region 14. A halogen gas containing chlorine (Cl) (for example, chlorine (Cl2), boron trichloride (BCl3), etc.) or a mixed gas prepared by adding ammonia (NH3) to carbon monoxide (CO) is used as the etching gas. In performing the etching, it is important to set the etching conditions so that the etching is stopped in the thin aluminum oxide film of the tunnel insulation layer 133 by raising the etching selectivity ratio between the storage layer 134 formed of the ferromagnetic material on the tunnel insulation layer 133 and the aluminum oxide of the tunnel insulation layer 133 to a value of not less than 10, or by lowering the etching speed.
Next, as shown in FIG. 3C, the remaining tunnel insulation layer (not shown), the magnetization fixed layer 132 composed of the ferromagnetic material layer as the lower layer, the antiferromagnetic material layer 131, and the barrier layer (not shown in this figure) are etched by a reactive ion etching technique using a photoresist as a mask, and a connection wiring 16 is formed. Thereafter, the resist mask is removed.
Subsequently, as shown in FIG. 4A, a fourth insulation film 44 is formed by building up a silicon oxide film in a thickness of 300 nm on the insulation film 43 so as to cover the TMR device 13, the connection wiring 16 and the like by a plasma CVD method, and thereafter the fourth insulation film 44 is provided with a connection hole 441 reaching the TMR device 13 by dry etching using a photoresist as a mask. In addition, connection holes (omitted in this figure) for connection to lower-layer wirings of peripheral circuits (the same layer as the landing pad for connection between the substrate and the TMR device) are also formed.
Next, as shown in FIG. 4B, a bit line 12 connected to the TMR device 13 through the connection hole 441, the wirings of the peripheral circuits (not shown in this figure), and a bonding pad region (omitted in this figure) are formed by a standard wiring forming technique. Further, a fifth insulation film 45 is formed by building up a plasma silicon nitride film on the whole surface of the fourth insulation film 44 in the manner of covering the bit line 12, and thereafter a bonding pad portion (not shown) is opened, to complete the LSI wafer process.
In this manufacturing method, as shown in FIG. 5, due to the presence of alignment errors between a mask pattern 71 (indicated by two-dotted chain line) for forming the TMR device region and a mask pattern 72 for forming the connection wirings, dimensional dispersions and the like, it is necessary to set the mask pattern 72 to be greater than the mask pattern 71 by ΔX=0.07 to 0.1 μm so that the surface of the TMR device 13 is not exposed at the time of forming the connection wirings. Even upon designing with a minimum dimension of design rule given to the TMR device, the connection wirings would be greater by two times of the alignment margin (i.e., 0.14 to 0.2 μm). Therefore, the memory cell obtained would be greater by 0.14 to 0.2 μm in the arrangement direction of the writing word lines 11.
In the MRAM cell comprised of one selection device and one TMR device or comprised of two selection devices and two TMR devices, the reduction of the size of the cell is an important factor for raising the degree of integration. As an example, the cell layout of the MRAM comprised of one selection device and one TMR device is shown in FIG. 6.
As shown in FIG. 6, the cell size is derived from the TMR device 13 and the TMR device 13, and is determined by the design rule for the connection wiring 16 used for connection between the TMR device 13 and the conductive layer (not shown) on the lower side thereof. Here, for simplification, the minimum dimension of the writing word line 11, the connection wiring 16, the TMR device 13, and the bit line 12 (indicated by two-dotted chain line) is denoted by F. In addition, a connection hole 433 is formed for connection between the connection wiring 16 and the conductive layer on the lower side thereof.
The formation of the TMR device portion is conducted in two stages: a first stage for patterning and etching of the TMR device 13, and a second stage for patterning and etching of the connection wiring 16. Since both etching steps are carried out by use of a gas for metal etching, where the mask pattern 72 constituting the etching mask at the time of forming the connection wiring is staggered from the TMR device 13 by, for example, ΔX and the TMR device 13 is partly exposed, as shown in FIG. 7, the portion of the TMR device 13 exposed out of the mask pattern 72 is also etched, whereby the shape of the TMR device 13 is changed. Since the shape dispersion of the TMR devices 13 has a great influence on the device characteristics (the writing characteristic such as to change the magnetization direction), the mask pattern 72 for forming the connection wiring for the TMR device 13 must be set to a size for covering an area larger than the area of the TMR device 13, taking into account the mask alignment errors, dimensional dispersions and the like.
As a result, there has been the problem that the cell size would be large, making it impossible to raise the degree of integration. As is clear from FIG. 6, the cell size is enlarged by ΔX in the arrangement direction of the bit lines 12 and by ΔX×2 in the arrangement direction of the writing word lines 11 which are arranged to be three-dimensionally orthogonal to the bit lines 12.